Field of the Invention
The invention relates to MOSFET devices and, in particular, to recessed access devices for semiconductor devices and methods of making the same.
Technical Background
Semiconductor devices employ access devices to store and retrieve data stored in memory circuits. The access devices may include semiconductor structures such as transistor devices, and can be in the form of planar or recessed access device structures. The gate electrode of an access device is biased, by an access device driver circuit, providing “on” and “off” states for the access device and facilitating the access and storage of data in the memory circuit utilizing the access devices. When the device is “on,” current is allowed to flow through the access device, and therefore the transistor is in inversion. When the device is “off,” current is supposed to be blocked from flowing through the access device, and therefore the transistor is in accumulation.
FIG. 1 illustrates a conventional planar access device (PAD) or transistor device, used with semiconductor memory circuits. A gate stack 60 is formed over a semiconductor substrate 50. The gate stack 60 includes a gate-oxide layer 62, a gate electrode 64, an insulator cap 66, and sidewall spacers 68. Source and drain regions 54 are located on either side of the gate stack 60 forming the transistor device.
FIG. 2 illustrates a conventional recessed access device (RAD) used with semiconductor memory circuits. The RAD structure includes a gate stack 70 formed in trenches of a semiconductor substrate 50. The gate stack 70 includes a gate-oxide layer 72, a gate electrode 74, an insulator cap 76, and sidewall spacers 78. Source and drain regions 54 are located on either side of the gate stack 70 forming the RAD device.
The PAD and RAD structures illustrated in FIGS. 1 and 2 may be used as access devices for memory circuits. As the dimensional requirements of semiconductor structures continue to diminish in size, fabrication processes are developed to accommodate the shrinking dimensions. For a memory circuit, utilizing either a PAD or RAD structure as the access device, there are three major undesirable leakage paths in the transistor: subthreshold leakage, gate induced drain leakage (GIDL), and junction leakage. Each leakage type occurs when the access device is in accumulation, or the “off” state. Subthreshold leakage is the leakage of charge between the source and drain of the access device and increases with smaller transistor dimensions, specifically the effective length of the gate in an access device. One way of reducing the subthreshold leakage is to apply a more negative voltage to the gate electrode of the access device in the “off” state. For example, in an “off” state, a negative voltage is applied to the PAD gate electrode 64 or the RAD gate electrode 74, illustrated in FIGS. 1 and 2, respectively. However, the application of a more negative voltage to the gate electrode results in higher GIDL current in the access device. Another way of reducing the subthreshold leakage is to apply a more negative voltage to the substrate 50. However, the application of a more negative voltage to the substrate results in increased junction leakage. Subthreshold leakage may also be decreased by employing a high work function difference between the source and drain regions and a gate electrode, for example, by employing a P+ gate and an N+ source/drain region. However, GIDL current increases in such cases.
Furthermore, the RAD gate stack 70, and the use of RAD gate stacks 70 with semiconductor devices, increases the effective length of a gate in an access device compared to the PAD gate stack 60. The increased length of the gate tends to decrease the amount of subthreshold leakage in the access device. However, the GIDL current from the RAD gate stack 70 is greater than the GIDL current of PAD gate stack 60. It is believed that the increased amount of GIDL loss in the RAD gate stack 70 is the result of the increased overlap of the source/drain regions 54 with the gate electrode 74.
Therefore, it is desirable to develop an access device for use with memory devices and other semiconductor devices that may be able to reduce subthreshold leakage, junction leakage, and gate induced drain leakage simultaneously. It is also desirable to develop processes for fabricating such devices using conventional semiconductor fabrication processes.